This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-166041, filed on Jun. 1, 2001, the entire contents of which are incorporated by reference.
The present invention relates to a semiconductor memory device having floating gates. Particularly, this invention relates to a semiconductor memory device having floating gates formed on a device-isolation region and a method of producing this type of semiconductor memory device.
A device-isolation region with a shallow trench, a shallow-trench isolation (termed STI hereinafter) region, is provided in device isolation process to meet the demands for scaling-down under a specific design rule for miniaturization of highly integrated semiconductor memory devices.
A known method of producing a semiconductor memory device is described with reference to FIGS. 1A to 1G, focusing on forming memory-cell sections.
As shown in FIG. 1A, STI regions 101 are formed in a semiconductor substrate 100, and then gate oxide films 102 are formed on the semiconductor substrate 100. Formed next are floating gates 103, each formed on a part of the corresponding gate oxide film 102 and STI region 101. A CVD silicon oxide film 104 is then formed on a part of each floating gate 103 by chemical vapor deposition (termed CVD hereinafter). Formed on each side wall of the CVD silicon oxide film 104 in the same way is a CVD silicon-oxide-film side wall 105.
Next, as shown in FIG. 1B, reactive ion etching (termed RIE hereinafter) is applied to provide a groove 106 in each STI region 101, having 50 nm in depth from the upper surface of each STI region 101 and makes thin films of the CVD silicon oxide films 104 and CVD silicon-oxide-film side walls 105.
The CVD silicon oxide films 104 and CVD silicon-oxide-film side walls 105 formed on the floating gates 103 are removed by HF paper cleaning, as shown in FIG. 1C.
Next, as shown in FIG. 1D, a gate-to-gate insulating film 107 of an ONO film having 20 nm in entire thickness is deposited over the entire device surface by low-pressure chemical vapor deposition (termed LP-CVD hereinafter). The ONO film is an insulating film having a three-layer structure of a silicon oxide film (O), a silicon nitride film (N) and another silicon oxide film (O), termed an inter-poly insulating film.
Deposited over the entire device surface by LP-CVD, as shown in FIG. 1E, is a P-type-impurity-doped polycrystalline silicon layer 108 having about 100 nm in thickness, followed by a tungsten silicide film 109 having about 50 nm in thickness deposited by sputtering. The polycrystalline silicon layer 108 and the tungsten silicide film 109 function as control gates for this semiconductor memory device. Deposited next on the tungsten silicide film 109 by LP-CVD is a silicon nitride film 110 having thickness in the range from 200 nm to 230 nm, for example.
The silicon nitride film 110 is made thin, as shown in FIG. 1F, by removing the film 110 by a certain thickness.
A structure of such semiconductor memory device and a method of producing such semiconductor memory device are shown for example in FIGS. 17 to 25 in Japanese Patent Application No. 11-350841 (Japanese Unexamined Patent Publication No. 2001-168306).
The known semiconductor memory device described above has the following drawbacks:
Metallic substances, if attached on an exposed surface of the semiconductor memory device during the process in FIG. 1C, could cause crystal defects, low reliability, and so on. The buried surface under the gate-to-gate insulating film 107 should be cleaned for preventing such phenomena to enhance insulating property. This is usually performed with dilute hydrofluoric acid effective for metal removal.
The dilute-hydrofluoric-acid cleaning etches a silicon oxide film equally in all directions. In detail, as shown in FIG. 1G, an enlarged view of a block Q in FIG. 1F, etching has advanced in a lateral direction over the exposed surface of the STI region 101 under the floating gate 103.
The advancement of etching forces the floating gate 103 to face the polycrystalline silicon 108 at two corners R and S via the gate-to-gate insulating film 107. Electric flux lines will converge at the corners R and S of the floating gate 103 toward the polycrystalline silicon layer 108 to increase electric field locally in accordance with the curvature radius of each corner.
Increase in electric field locally converged at the corners R and S of the floating gate 103 and applied to the gate-to-gate insulating film 107 while the memory cell is operating for writing or erasing could cause a low insulating property. This leads to a high probability of memory-cell writing/erasing property lowering or memory-cell threshold-level variation.
Dielectric breakdown or increased leak current could also be caused under stresses due to electric field applied and converged on the gate-to-gate insulating film 107 in memory-cell writing, erasing or charging.
A semiconductor memory device having at least one floating gate according to the first aspect of the present invention includes: a semiconductor substrate; at least one device-isolation region buried in the semiconductor substrate, having a top surface protruding from a top surface of the semiconductor substrate, the top surface of the device-isolation region having a concave section that has a depression thereon; at least one gate-insulating film formed on the semiconductor substrate; a first gate formed on the gate-insulating film, the device-isolation region and the depression; a gate-to-gate insulating film formed on the first gate and in the concave section and the depression of the device-isolation region; and a second gate formed on the gate-to-gate insulation film, the depression being filled with the second gate.
Moreover, a semiconductor memory device having floating gates according to the second aspect of the present invention includes: a semiconductor substrate; at least one device-isolation region buried in the semiconductor substrate, having a top surface protruding from a top surface of the semiconductor substrate, the top surface of the device-isolation having a concave section that has a depression thereon; at least one gate-insulating film formed on the semiconductor substrate; a plurality of first gates formed on the gate-insulating film, the device-isolation region and the depression, the first gates being isolated from each other on the device-isolation region; a gate-to-gate insulating film formed on the first gates and in the concave section and the depression of the device-isolation region, the first gates being isolated from each other by the gate-to-gate insulating film; and a second gate formed on the gate-to-gate insulation film, the depression area being filled with the second gate.
Furthermore, a method of producing a semiconductor memory device having floating gates according to the third aspect of the present invention forms at least one device-isolation region and a gate-insulating film on a semiconductor substrate; forms a first gate material on the device-isolation region and the gate-insulating film; forms first gate electrodes by separating the first gate material into two gate materials, the separated materials being left on the device-isolation region; provides a concave section on the device-isolation region, the concave section being narrower than a distance between the separated first gate electrodes; provides a depression in the device-isolation region under the first gate electrodes and at edges of the concave section on the device-isolation region; forms a gate-to-gate insulating film on the concave section on the device-isolation region and the first gate electrodes, the depression in the device-isolation region being filled with the gate-to-gate insulating film; and forms a second gate electrode on the gate-to-gate insulation film.
Moreover, a method of producing a semiconductor memory device having floating gates according to the fourth aspect of the present invention forms a gate-insulating film and then a first gate material on a semiconductor substrate; provides at least one groove through the first gate material, the gate-insulating film and a part of the semiconductor substrate; fills the groove with an insulating material to form a device-isolation region having a top surface higher than a top surface of the first gate material; forms a second gate material on the first gate material and the device-isolation region; forms second gate electrodes by separating the second gate material into two gate materials, the separated materials being left on the device-isolation region; provides a concave section on the device-isolation region, the concave section being narrower than a distance between the separated second gate electrodes; provides a depression in the device-isolation region under the second gate electrodes and at edges of the concave section on the device-isolation region; forms a gate-to-gate insulating film on the concave section on the device-isolation region and the second gate electrodes, the depression in the device-isolation region being filled with the gate-to-gate insulating film; and forms a third gate electrode on the gate-to-gate insulating film.